Input buffers often use a CMOS inverter. An example of a conventional inverter gate type input buffer is shown in FIG. 1. A nominal supply voltage is used at the input stage. The trip point of the input buffer depends on the supply voltage as well as temperature and process skew. Variations in the supply voltage, temperature or process skew can increase the trip point which can result in an increase in the propagation delay on the input signal rising edge and a decrease in the propagation delay on the input signal falling edge. If the signal has to be clocked into a register, this variation in propagation delay will affect the set up and hold times to the register. In particular if the propagation delay is increased the register will take longer to set up. Higher frequency applications typically have to meet tighter set up and hold specifications than lower frequency applications. For example, this is true for cache RAM which must meet increasingly tighter set up and hold specifications for the latest microprocessor applications.
One proposed solution is to provide a reference voltage to stabilize the trip point of the input buffer so that it is not sensitive to variations in supply voltage, temperature or process skew. An example of a suitable circuit is shown in FIG. 2. A CMOS reference voltage source (not shown) is used which is designed to reject variations in the supply voltage (Vcc), temperature and process skew. The reference voltage source generates a reference voltage (Vref) which is supplied to a reference branch of the input buffer, as will be described in detail below.
The voltage referenced input buffer comprises an input branch 21 and a reference branch 22. Transistor 23 and transistor 24 of the reference branch 22 form an inverter with its input voltage fixed by the reference voltage Vref. Transistor 25 is diode connected and derives a control signal for a PMOS transistor 26 within the input branch 21. By design, transistor 23 and transistor 24 of the reference branch 22 are kept in the saturated region throughout the range of the supply voltage. This ensures that the reference branch trip point is determined solely by the reference voltage. The current in the input branch 21 is set by a loop consisting of transistor 23, transistor 25, transistor 26 and transistor 27 to be a scaled-up copy of the current in the reference branch 22, provided the input voltage equals the reference voltage. The circuit's symmetry ensures that transistor 27 and transistor 28 within the input branch 21 also operate in the saturated region, just like the corresponding components transistor 23 and transistor 24 within the reference branch 22. Accordingly, the trip point of the input branch 21 is constrained by the reference voltage, irrespective of changes in the supply voltage. The output of the input branch is drawn from a node between PMOS transistor 26 and NMOS transistor 28. This configuration can be seen as a differential-type input stage which compares the supply voltage with a reference voltage and rejects undesirable variations in the supply voltage.
The main benefit of such an input buffer is that it provides a stable trip point, thus allowing set up and hold specifications to be met with better margins. However, the voltage reference generator associated with such an input buffer draws a large standby current (I.sub.sb), which is undesirable.
Our co-pending U.S. patent application with Ser. No. 08/874,006, now U.S. Pat. No. 5,848,014, the contents of which which are incorporated herein by reference, discloses a controllable sleep/power-down mode for a input buffer. This enables an input buffer to exist in a state in which it draws no standby current when it is not reading or writing data from or into a memory device.